FPGA implementation of the HL-LHC CMS Drift Tubes Level-1 Trigger Algorithm
por
Sala Maria de Maeztu (Edificio 2)
The HL-LHC has motivated a generalized upgrade in electronic systems across all experiments. In the new electronics architecture for the CMS Drift Tubes detector, the trigger generation moves from on-detector ASICs to the back-end, to be carried out by top-range FPGAs. The new algorithm aims to deliver full-resolution, offline-grade performance in the reconstruction of muon segments. To achieve this objective, meeting the latency and data rate requirements, a high-speed, highly-pipelined FPGA design with several optimizations has been developed. The architecture and performance of this algorithm, as well as the challenges encountered during implementation and the solutions adopted, will be described.
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