Ponente
Descripción
In this talk, we present the progress on development of CMOS-based front-end application-specific integrated circuits (ASICs) for charge and light readout undertaken at Brookhaven National Laboratory. This design evolves from the LArASIC chip manufactured in 0.18 µm, that has been selected for charge readout in the liquid argon time protection chamber (LArTPC) in the phase I of DUNE. LArASIC is the first component in a 3-ASIC readout chain, realizing amplification with transformation of charge to a pulse-shaped voltage waveform. DUNE explores neutrino oscillations, interactions and transformations and is carried out at liquid argon temperatures (i.e., 87 K). The efforts aim at translation and introduction of the required modifications of the legacy design to a scaled CMOS technology, i.e., 65 nm, that can be used in future experiments. The front-end ASIC is designed to have two amplification stages with a programmable gain followed by a